Upasna Vishnoi and Tobias G Noll
The CORDIC algorithm is frequently used in many applications and dedicated CORDIC macros are attractive components for SoCs e.g., as hardware accelerators to Application-Specific Instruction-set Processors. Therefore, there is a wide variety of CORDIC specifications. In order to achieve high area and energy efficiency for a given specification, a systematic exploration of the design space is required. Due to the features of today’s deep-submicron CMOS technologies, there are strong interactions between the design levels which makes a quantitative optimization challenging. In this contribution, an attractive approach based on algebraic cost models is described, which allows for exploring the design space with adequate accuracy and in reasonable time. The benefits from this approach are demonstrated by an evaluation for different exemplary CORDIC specifications.
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